1 idt54/74fct162511at/ct fast cmos 16-bit registered/latched transceiver military and industrial temperature ranges september 2009 idt54/74fct162511at/ct military and industrial temperature ranges fast cmos 16-bit registered/latched transceiver with parity description: the fct162511t 16-bit registered/latched transceiver with parity is built using advanced dual metal cmos technology. this high-speed, low-power transceiver combines d-type latches and d-type flip-flops to allow data flow in transparent, latched, or clocked modes. the device has a parity generator/ checker in the a-to-b direction and a parity checker in the b-to-a direction. error checking is done at the byte level with separate parity bits for each byte. separate error flags exits for each direction with a single error flag indicating an error for either byte in the a-to-b direction and a second error flag indicating an error for either byte in the b-to-a direction. the parity error flags are open drain outputs which can be tied together and/or tied with flags from other devices to form a single error flag or interrupt. the parity error flags are enabled by the oexx control pins allowing the designer to disable the error flag during combinational transitions. the control pins leab, clkab, and oeab control operation in the a-to-b direction while leba, clkba, and oeba control the b-to-a direction. gen / chk is only for the selection of a-to-b operation. the b-to-a direction is always in checking mode. the odd/ even select is common between the two directions. except for the odd/ even control, independent operation can be achieved between the two directions by using the corresponding control lines. gen/chk latch/ register byte parity generator/ checker latch/ register byte parity checking b0-15 a0-15 pa1,2 pb1,2 perb leab clkab oeab oeba pera leba clkba parity, data parity, data parity, data data (open drain) (open drain) parity odd/even 16 18 18 18 2 the idt logo is a registered trademark of integrated device technology, inc. ? 2009 integrated device technology, inc. dsc-2916/4 features: ? 0.5 micron cmos technology ? typical t sk(o) (output skew) < 250ps, clocked mode ? low input and output leakage 1a (max) ? esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) ?v cc = 5v 10% ? balanced output drivers: ? 24ma (industrial) ? 16ma (military) ? series current limiting resistors ? generate/check, check/check modes ? open drain parity error allows wire-or ? available in the following packages: ? industrial: ssop, tssop ? military: cerpack functional block diagram
2 military and industrial temperature ranges idt54/74fct162511at/ct fast cmos 16-bit registered/latched transceiver block diagram a 8 - a 15 gen/chk oeab clkba leba clkab a 0 - a 7 leab b 0 - b 7 d c c d oeba d c b 8 - b 15 d c c d pb 2 pa 2 c d c d p c d c d perb d c d c pb 1 pa 1 c d c d p (open drain) d c d c d c d c d c d c d c odd/even (open drain) pera p p i o i o
3 idt54/74fct162511at/ct fast cmos 16-bit registered/latched transceiver military and industrial temperature ranges ssop/ tssop/ cerpack top view pin configuration gen/chk b 0 b 1 gnd b 2 b 3 v cc b 4 b 6 pb 1 b 7 perb gnd b 8 b 5 b 9 b 11 v cc b 12 b 10 clkab b 14 b 13 b 15 gnd pb 2 clkba odd/even oeab leab pa 1 gnd a 0 a 1 v cc a 2 a 3 a 5 a 4 a 6 a 7 gnd a 10 pera a 8 v cc a 9 pa 2 a 12 a 11 a 14 gnd a 15 leba a 13 oeba 47 37 38 39 40 41 42 43 44 45 46 33 34 35 36 56 55 49 50 51 52 53 54 48 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 11 21 22 23 24 29 30 31 32 25 26 27 28 symbol description max unit v term (2) terminal voltage with respect to gnd ?0.5 to 7 v v term (3) terminal voltage with respect to gnd ?0.5 to v cc +0.5 v t stg storage temperature ?65 to +150 c i out dc output current ?60 to +120 ma absolute maximum ratings (1) (1) (1) (1) (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. all device terminals except fct162xxx output and i/o terminals. 3. output and i/o terminals for fct162xxx. symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 3.5 6 pf c i/o i/o capacitance v out = 0v 3.5 8 pf c o open drain v out = 0v 3.5 6 pf capacitance capacitance (t a = +25c, f = 1.0mhz) pin description pin names description oeab a-to-b output enable input (active low) oeba b-to-a output enable input (active low) leab a-to-b latch enable input leba b-to-a latch enable input clkab a-to-b clock input clkba b-to-a clock input a x a-to-b data inputs or b-to-a 3-state outputs b x b-to-a data inputs or a-to-b 3-state outputs pera parity error (open drain) on a outputs perb parity error (open drain) on b outputs pax (1) a-to-b parity input, b-to-a parity output pbx b-to-a parity input, a-to-b parity output odd/ even parity mode selection input gen /chk a to b port generate or check mode input note: 1. the pax pin input is internally disabled during parity generation. this means that when generating parity in the a to b direction there is no need to add a pull up resistor to guarantee state. the pin will still function properly as the parity output for the b to a direction.
4 military and industrial temperature ranges idt54/74fct162511at/ct fast cmos 16-bit registered/latched transceiver notes: 1. conditions shown are for gen /chk = h, oeab = l, oeba = h. 2. a-to-b parity checking is shown. b-to-a parity checking is similar but uses oeba = l, oeab = h and errors will be indicated on pera . 3. in parity checking mode the parity bits will be transmitted unchanged along with the corresponding data regardless of parity errors (pb1 = pa1). 4. the response shown is for leab = h. if leab = l then clkab will control as an edge triggered clock. 5. conditions shown are for the byte a0?a7 and pa1. the byte a8?a15 and pa2 is similiar. 6. the parity error flag perb is a combined flag for both bytes a0?a7 and a8?a15. if a parity error occurs on either byte perb will go low. perb is an open drain output which must be externally pulled up to achieve a logic high. notes: 1. conditions shown are for gen /chk = l, oeab = l, oeba = h. 2. a-to-b parity checking is shown. b-to-a is capable of parity checking while a-to-b is performing generation. b-to-a will not generate parity. 3. the response shown is for leab = h. if leab = l then clkab will control as an edge triggered clock. 4. conditions shown are for the byte a?a7. the byte a8?a15 is similiar but will output the parity on pb2. 5. the error flag perb will remain in a high state during parity generation. function table (1, 4) notes: 1. a-to-b data flow is shown. b-to-a data flow is similar but uses oeba , leba, and clkba. 2. output level before the indicated steady-state input conditions were established. 3. output level before the indicated steady-state input conditions were established, provided that clkab was high before leab went low. 4. h = high voltage level l = low voltage level x = don't care z = high-impedance = low-to-high transition inputs outputs oeab leab clkab ax bx hxxxz lhxll lhxhh ll ll ll hh lllxb (2) llhxb (3) a0 ? a7 number of inputs that are high odd/ even pb1 1, 3, 5 or 7 l h 1, 3, 5 or 7 h l 0, 2, 4, 6 or 8 l l 0, 2, 4, 6 or 8 h h a 0 ? a 7 and p a1 (5) number of inputs that are high odd/ even perb 1, 3, 5, 7 or 9 l l 1, 3, 5, 7 or 9 h h (6) 0, 2, 4, 6 or 8 l h (6) 0, 2, 4, 6 or 8 h l function table (parity checking) (1, 2, 3, 4) function table (parity generation) (1, 2, 3, 4, 5)
5 idt54/74fct162511at/ct fast cmos 16-bit registered/latched transceiver military and industrial temperature ranges symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level guaranteed logic high level 2 ? ? v v il input low level guaranteed logic low level ? ? 0.8 v i ih input high current (input pins) (5) v cc = max. v i = v cc ?? 1a input high current (i/o pins) (5) ?? 1 i il input low current (input pins) (5) v i = gnd ? ? 1 input low current (i/o pins) (5) ?? 1 i ozh high impedance output current v cc = max. v o = 2.7v ? ? 1a i ozl (3-state output pins) (5) v o = 0.5v ? ? 1 v ik clamp diode voltage v cc = min., i in = ?18ma ? ?0.7 ?1.2 v i os short circuit current v cc = max., v o = gnd (3) ?80 ?140 ?250 ma v h input hysteresis ? ? 100 ? mv i ccl quiescent power supply current v cc = max. ? 5 500 a i cch v in = gnd or v cc i ccz dc electrical characteristics over operating range following conditions apply unless otherwise specified: industrial: t a = ?40c to +85c, v cc = 5.0v 10%; military: t a = ?55c to +125c, v cc = 5.0v 10% notes: 1. for conditions shown as min. or max., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. not more than one output should be shorted at one time. duration of the test should not exceed one second. 4. duration of the condition can not exceed one second. 5. the test limit for this parameter is 5a at t a = ?55c. output drive characteristics symbol parameter test conditions (1) min. typ. (2) max. unit i odl output low (i/o pins) v cc = 5v, v in = v ih or v il , v o = 1.5v (3) 60 115 200 ma current (open drain) ? 250 ? ma i odh output high current v cc = 5v, v in = v ih or v il , v o = 1.5v (3) ?60 ?115 ?200 ma i off output power off leakage current v cc = 0, v o 5.5v ? ? 1 a (open drain) (5) v oh output high voltage (i/o pins) v cc = min. i oh = ?16ma mil 2.4 3.3 ? v v in = v ih or v il i oh = ?24ma ind v ol output low (i/o pins) v cc = min. i ol = 16ma mil ? 0.3 0.55 v voltage v in = v ih or v il i ol = 24ma ind (open drain) i ol = 48ma mil ? 0.3 0.55 v i ol = 64ma ind
6 military and industrial temperature ranges idt54/74fct162511at/ct fast cmos 16-bit registered/latched transceiver symbol parameter test conditions (1) min. typ. (2) max. unit i cc quiescent power supply current v cc = max. all other input pins ? 0.5 1.5 ma ttl inputs high v in = 3.4v (3) parity input pins (pax, pbx) ? 1 2.5 i ccd dynamic power supply v cc = max. v in = v cc ? 75 120 a / current (4) outputs open v in = gnd mhz oeab = gnd, oeba = v cc one input togging 50% duty cycle i c total power supply current (6) v cc = max. v in = v cc ? 0.8 1.7 ma outputs open v in = gnd f cp = 10mhz (clkab) 50% duty cycle oeab = gnd, oeba = v cc leab = gnd v in = 3.4v ? 1.3 3.2 one bit toggling v in = gnd f i = 5mhz 50% duty cycle v cc = max. v in = v cc ? 3.8 6.5 (5) outputs open v in = gnd f cp = 10mhz (clkab) 50% duty cycle oeab = gnd, oeba = v cc leab = gnd v in = 3.4v ? 9 21.8 (5) eighteen bits toggling v in = gnd f i = 2.5mhz 50% duty cycle power supply characteristics notes: 1. for conditions shown as min. or max., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. per ttl driven input (v in = 3.4v). all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + i cc d h n t + i ccd (f cp n cp /2 + fini) i cc = quiescent current (i ccl , i cch and i ccz ) i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) n cp = number of clock inputs at f cp fi = input frequency ni = number of inputs at fi
7 idt54/74fct162511at/ct fast cmos 16-bit registered/latched transceiver military and industrial temperature ranges fct162511at fct162511ct ind. mil. ind. mil . symbol parameter condition (1) min. (2) max. min. (2) max. min. (2) max. min. (2) max. unit t plh propagation delay, pax to pbx c l = 50pf 1.5 5 1.5 5.3 1.5 4.2 1.5 4.5 ns t phl ax to bx or bx to ax, pbx to pax r l = 500 t plh propagation delay gen /chk low 1.5 7.5 1.5 8 1.5 6.5 1.5 6.8 ns t phl ax to pbx t plh (3) propagation delay 1.5 9 1.5 9 1.5 7.5 1.5 7.8 ns t phl ax to perb, pax to perb 1.5 8 1.5 8 1.5 6.5 1.5 6.8 ns t plh (3) propagation delay 1.5 9 1.5 9 1.5 7.5 1.5 7.8 ns t phl bx to pera, pbx to pera 1.5 8 1.5 8 1.5 6.5 1.5 6.8 ns t plh propagation delay t phl leba to ax and pax 1.5 5.6 1.5 6 1.5 5.3 1.5 5.5 ns leab to bx and pbx t plh (3) propagation delay 1.5 7 1.5 7 1.5 6 1.5 6.3 ns t phl leba to pera , leab to perb 1.5 6 1.5 6 1.5 5 1.5 5.3 ns t plh propagation delay t phl clkba to ax and pax 1.5 5.6 1.5 6 1.5 5.3 1.5 5.5 ns clkab to bx and pbx t plh (3) propagation delay 1.5 7 1.5 7 1.5 6 1.5 6.3 ns t phl clkba to pera clkab to perb 1.5 6 1.5 6 1.5 5 1.5 5.3 ns t pzh output enable time t pzl oeba to ax and pax 1.5 6 1.5 6.5 1.5 5.6 1.5 5.8 ns oeab to bx and pbx t phz output disable time t plz oeba to ax and pax 1.5 5.6 1.5 6 1.5 5.2 1.5 5.5 ns oeab to bx and pbx t plz (3) parity error enable 1.5 6 1.5 6.3 1.5 6 1.5 6.3 ns t pzl oeba to pera , oeab to perb 1.5 6 1.5 6.3 1.5 6 1.5 6.3 ns t plh (3) odd/ even to perx 1.5 10 1.5 10 1.5 10 1.5 10 ns t phl 1.5 10 1.5 10 1.5 10 1.5 10 ns t plh odd/ even to pbx 1.5 10 1.5 10 1.5 10 1.5 10 ns t phl switching characteristics over operating range (propagation delays) notes: 1. see test circuits and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. on open drain outputs t plh is measured at v out = v ol + 0.3v.
8 military and industrial temperature ranges idt54/74fct162511at/ct fast cmos 16-bit registered/latched transceiver fct162511at fct162511ct ind. mil. ind. mil. symbol parameter test conditions (1, 3) min. max. min. max. min. max. min. max. unit t su set-up time gen /chk low pbx valid c l = 50pf 4 ? 4 ? 3 ? 3.5 ? ns high or low pbx not valid r l = 500 3? 3?3?3?ns ax to clkab gen /chk high perb valid 4 ? 4 ? 3 ? 3 ? ns perb not valid 3 ? 3 ? 3 ? 3 ? ns t su set-up time gen /chk high perb valid 4 ? 4 ? 3 ? 3 ? ns pax to clkab perb not valid 3 ? 3 ? 3 ? 3 ? ns t su set-up time pera valid 4 ? 4 ? 3 ? 3 ? ns bx to clkba, pera not valid 3 ? 4 ? 3 ? 3 ? ns pbx to clkba t su set-up time clkab low pbx valid 3.5 ? 3.5 ? 3 ? 3 ? ns ax to leab gen /chk low pbx not valid 3 ? 3 ? 3 ? 3 ? ns clkab low perb valid 3.5 ? 3.5 ? 3 ? 3 ? ns gen /chk high perb not valid 3 ? 3 ? 3 ? 3 ? ns clkab high pbx valid 3.5 ? 3.5 ? 3 ? 3 ? ns gen /chk low pbx not valid 3 ? 3 ? 3 ? 3 ? ns clkab high perb valid 3.5 ? 3.5 ? 3 ? 3 ? ns gen /chk high perb not valid 3 ? 3 ? 3 ? 3 ? ns t su set-up time clkab low perb valid 3.5 ? 3.5 ? 3 ? 3 ? ns pax to leab gen /chk high perb not valid 3 ? 3 ? 3 ? 3 ? ns clkab high perb valid 3.5 ? 3.5 ? 3 ? 3 ? ns gen /chk high perb not valid 3 ? 3 ? 3 ? 3 ? ns t su set-up time clkba low pera valid 3.5 ? 3.5 ? 3 ? 3 ? ns bx to leba pera not valid 3 ? 3 ? 3 ? 3 ? ns pbx to leba clkba high pera valid 3.5 ? 3.5 ? 3 ? 3 ? ns pera not valid 3 ? 3 ? 3 ? 3 ? ns t sk(o) output skew (4) ? 0.5 ? 0.5 ? 0.5 ? 0.5 ns switching characteristics over operating range (set up times) fct162511at fct162511ct ind. mil. ind. mil. symbol parameter condition (1) min. max. min. max. min. max. min. max. unit t h hold time high or low ax to leab, bx to leba c l = 50pf 1 ? 1 ? 1 ? 1 ? ns t h hold time high or low pax to leab r l = 500 1?1?1? 1?ns t h hold time high or low pbx to leba 1 ? 1 ? 1 ? 1 ? ns t h hold time ax to clkab, pax to clkab 1 ? 1 ? 0 ? 0 ? ns t h hold time bx to clkba, pbx to clkba 1 ? 1 ? 0 ? 0 ? ns t w leab or leba pulse width high (2) 3?3?3? 3?ns t w clkab or clkba pulse width high or low (2) 3?3?3? 3?ns switching characteristics over operating range (hold times) notes: 1. see test circuits and waveforms. 2. this parameter is guaranteed but not tested. 3. "not valid" means the set-up time indicated is not sufficient to assure proper functioning of this output; however, the set-u p time indicated will assure proper functioning of the a to b or b to a port respective to the indicated direction. 4. skew between any two outputs of the same package, switching in the same direction, excluding perx in clocked mode, and pxx (parity bits) and perx in transparent/ latched mode. this parameter is guaranteed by design.
9 idt54/74fct162511at/ct fast cmos 16-bit registered/latched transceiver military and industrial temperature ranges pulse generator r t d.u.t. v cc v in c l v out 50pf 500 500 7.0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h preset clear clock enable etc. high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open v ol 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable v oh test circuits and waveforms propagation delay test circuits for all outputs enable and disable times set-up, hold, and release times pulse width test switch open drain disable low closed enable low all other tests open switch position definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. notes: 1. diagram shown for input control enable-low and input control disable-high. 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns.
10 military and industrial temperature ranges idt54/74fct162511at/ct fast cmos 16-bit registered/latched transceiver ordering information xx temp. range xxxx device type xx package x process pvg pag industrial options shrink small outline package - green thin shrink small outline package - green 18-bit registered/latched transceiver 54 74 55 c to +125 c 40 c to +85 c 162 double-density, 5 volt, balanced drive e military options cerpack blank b industrial mil-std-883, class b fct xxx family 511at 511ct corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 logichelp@idt.com san jose, ca 95138 fax: 408-284-2775 www.idt.com datasheet document history 09/06/09 pg.6 updated the ordering information by removing the "idt" notation and non rohs part.
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